1. Field of the Invention
This invention relates to analog-to-digital converters. More particularly, this invention relates to cascaded multi-stage converters wherein each stage develops a corresponding part of the final digital output signal. The embodiments described hereinbelow utilize converter stages of the parallel type.
2. Brief Description of the Prior Art
Parallel or "flash" converters of various designs have been available for some time, and have speed of conversion as their principal goal. Conventional designs of this type for developing high-resolution outputs, such as 8 or 10 bits, have the disadvantage of requiring considerable circuitry, especially including a large number of comparators with associated logic. One approach to reducing the number of comparators is shown in U.S. Pat. No. 4,270,118 (Brokaw).
Still another design approach is to employ a successive series of stages (or cycles of operation) each arranged to develop a digital output of limited scope, e.g. 3 bits, and to produce from each stage (or cycle of operation) an analog residue signal as the input for the next stage (or cycle). In this way, a high-resolution output can be developed by combining the digital outputs of the several stages or cycles, which are sometimes referred to as sub-ranging stages or cycles. An example of this kind of converter is shown in U.S. Pat. No. 4,814,767 (Fernandes et al).
A major limitation of multi-stage ADC architectures results from the need for interstage amplification, particularly when the overall resolution exceeds about 9 bits. Such amplification is for the purpose of raising the residue of one conversion to a level which can be digitized by the next subsequent stage. In present designs, the gain of such amplification must be quite precisely controlled, in order to produce an accurate digital output.
The need for accurate amplification can be understood from consideration of the diagram of FIG. 1. This diagram shows a prior art multi-stage ADC having a first A/D stage 20, a DAC 22, and a summation circuit 24 to produce a residue signal. This residue signal is amplified by an interstage gain block 26 driving a second A/D stage 28. The digital outputs of the two A/D stages are combined to develop the final digital output.
In the system of FIG. 1, the size of one step of the DAC 22, when multiplied by the interstage gain, must exactly match the full-scale range of the second A/D stage. For example, if the complete converter is a 10-bit ADC comprised of a 5-bit DAC and two 5-bit A/D stages, and if the A/D stages have a 2-volt full-scale range, the residue into the interstage gain block 26 will be .+-.0.5 LSB at the 5-bit level, or .+-.1 V/32=31.25 mV. This must be amplified to provide .+-.1 volt full-scale, so a gain of 32 is required. This will provide from the second A/D stage 32 full codes between every threshold of the first stage. If, for example, the gain were only half of that required, there would be only 16 codes available at the second stage, so the converter performance would suffer significantly.
Various techniques have been devised to minimize problems from interstage gain inaccuracies. For example, the prior art has used so-called reference refreshing, error averaging, and self-calibration. Efforts also have been directed to improving gain accuracy, as by laser trimming of amplifier components. However, these techniques have not satisfactorily solved the problem.